The present disclosure is related to solid-state devices such as thin-film transistors, and more specifically to methods of forming such devices utilizing a self-aligning technique.
Current methods for manufacturing arrays of amorphous silicon thin film transistors (a-Si:H TFTs) typically begin with the deposition of a metal on the substrate on which a layer of a-Si:H is deposited. Additional layers of conducting and insulating materials are formed and patterned by photolithographic processes to create source, gate and drain regions for each TFT. These photolithographic processes typically involve the deposition of layers of photosensitive or photoresistive materials. The photoresistive materials are exposed through a mask, developed to remove portions of the materials, then the structure is etched to remove portions of the conducting and/or insulating layers not protected by the remaining photoresistive materials, to thereby form electrically connected and isolated or semi-isolated regions. Through multiple photolithographic and deposition steps, an array of layered semiconductor devices and interconnections may be formed on the transmissive substrate.
More specifically, a typical TFT 10, for example of the type shown in FIG. 10, comprises a source region 12 and drain region 14 formed over a dielectric layer 16, a semiconductive layer 18, and a gate region 20, all formed over a substrate 22. In order for current to flow in a channel in layer 18, there must be an amount of overlap, x1, x2, between the lateral edges of source region 12 and drain region 14 on the one hand, and gate region 20 on the other hand. A certain amount of such an overlap is required in order to provide conductivity between the source/drain and channel (for the injection of carriers). However, too much overlap results in parasitic capacitance between the gate region and the source/drain regions, resulting is device switching speed degradation and latency.
A number of techniques have been developed for creating self-aligned structures, for example using the gate region 20 as a mask when exposing photocurable etch resist, doing laser recrystallization, etc. However, it has heretofore been difficult to form the desired overlap x1, x2, using such techniques.